Designers of integrated circuits such as application specific integrated circuits (ASICs) are often confronted with having to make design trade-offs in their product to support the wide range of requirements of their customers. One type of design trade-off is providing input or output (I/O) cells in the ASIC that meet both, functional performance requirements, and electromagnetic compatibility performance requirements.
Functional requirements include performance characteristics such as input sensitivity, output drive capacity, output slew rate, and the like, which are needed to ensure that the IC interfaces with, and operates reliably, in its end product. Electromagnetic compatibility (EMC) requirements include such characteristics as suppression of spurious emissions of electromagnetic interference (EMI), and immunity from external sources of EMI and electrical transients such as electrical fast transient burst interference (EFT/B) and electrostatic discharge (ESD).
Many design tradeoffs exist when designing an I/O cell preferentially emphasizing EMC performance or emphasizing functional performance. In most situations, a one-size-fits-all I/O cell is simply not feasible. For instance, EMI suppression, whether for suppressing EMI and fast transients into, or out of, the IC, typically involves low-pass filtering I/O signals. Such low-pass filtering can adversely affect many important functional characteristics, such as the slew rate and potentially the drive capacity for output drivers. Likewise, for input circuits, the filtering can affect their sensitivity, impedance matching to the source, and input signal bandwidth.
Protection against transient spikes such as ESD typically involves implementing design techniques that can also adversely affect the functional performance in generally the same ways as the filtering techniques. A variety of ESD protection techniques for ICs are known, including placing impedances in series with the input or output lines to slow down and attenuate the ESD, or placing breakdown devices such as Zener diodes on the input or output lines to redirect a portion of the ESD to the power or ground nodes. Furthermore, because ESD events can have amplitudes in the thousands of Volts, chip-level ESD protection may also include layout and certain device design features, such as device sizing, separation, and isolation between devices such as the use of separate wells and trenches in the substrate, as described, for example in U.S. Pat. No. 7,250,660. All of these protection techniques can limit the functional performance of I/O cells.
Another important drawback associated with I/O cells having increased EMC-related performance is the difficulty or inability to support analog bypass lines or test points, which provide an ability to selectively bypass portions of the I/O circuitry. Bypass lines may be useful in a variety of instances, including in manufacturing testing and in system troubleshooting. Typically, bypass lines are enabled or disabled using a programmable electronic switch. Even with the switch opened, bypass lines can nevertheless present a path, via parasitic effects such as capacitive coupling, for EMI or transients to be carried past filters or other suppression circuitry. Moreover, for ESD immunity, the electronic switch must be designed to withstand ESD events, presenting a number of challenges to IC designers. The desired level of EMC performance can be thus difficult to achieve for I/O cells having bypass lines.
U.S. Pat. No. 6,327,125, discloses an IC with ESD-protective circuitry for use in testing, packaging, shipping, and installation into a system. The protective circuitry is disconnected via a programming step of blowing fuses. This approach removes the ESD protection prior to operation of the IC; thus, the system in which the IC is installed must provide sufficient ESD protection external to the IC to protect the IC. The approach of the '125 patent therefore does not address the needs of customers who require ESD or other EMC-related protection to be built into the IC, and has the disadvantage of requiring a special programming step.
U.S. Pat. No. 7,251,805 discloses manufacturing a “mega-ASIC” with excessive hardware functionality, only a portion of which is actually enabled in any operational ASIC. The different functional blocks can be disabled or enabled by a programming step prior to, or after packaging using FLASH memory, and the bonding pads of the device are connected to the appropriate functional blocks using programmable switches such as fuses or anti-fuses. A drawback of the mega-ASIC approach is the extra programming step required to configure the device, which represents an additional cost of manufacture.
Published U.S. Patent Application No. 2007/0170451, discusses a solution for bypassing a voltage regulator device in an IC by providing different bonding pads for hard wiring each IC power pin to either an input node or an output node of a corresponding voltage regulator device. This arrangement provides an IC that is configurable during the wire bonding process to operate at a higher voltage (enabling and connecting the voltage regulators), or at lower voltage (bypassing the voltage regulators altogether) without a programming step. However, while the '451 publication offers a technique for selectively wiring an IC pin to one node or to another node as a bypass, it does not address any of the challenges associated with the EMC-related trade-offs applicable to input or output cells discussed above.
While these approaches have addressed certain aspects of the challenges in designing ICs, these approaches are either too selective or tend to require additional programming or design solutions. A more effective and efficient solution is needed for managing the EMC performance design tradeoffs when designing ICs.